This invention relates to an error correcting system employing an error correction circuit which corrects errors included in the digital data, and in particular to an improvement of such a system in suppressing wrong error correction to be caused by erroneous operation of the error correction circuit itself.
Because of its intrinsically small redundancy, the information of digital data is subjected to a great change even by a single bit error. It is, therefore, important to take countermeasures against bit errors.
So far, for removing bit errors, there has been used such a technique that makes the data redundant by adding a certain bit or bits thereto, detects bit errors by checking the thus-obtained redundant data, and corrects the bit errors. One example is the so-called parity check technique. This technique can easily detect bit errors, but is inadequate for real time processing because a special processing for obtaining correct data, for example, retransmission of data, is necessary. Another example of the error correction technique is the so-called ECC (Error correcting code) technique. For details, refer, for example, to the articles of R. W. Hamming, "Error Detecting and Error Correcting Codes", The Bell System Technical Journal Vol. XXVI, No. 2, April, 1950, pp. 147-160, and M. Y. Hsiao; "A class of optimal Minimum Odd-weight-column SEC-DED Codes, IBM Journal of Research and Development, July, 1970, pp. 395-401. An error correction circuit, such as that based on ECC technique, enables real time data correction. However, the error correction circuit cannot detect erroneous operation of itself, and therefore, if the erroneous operation occurs, the correct data is made erroneous and destroyed. For avoiding such a problem, conventionally used is a parallel check system which is provided with two or three sets of identical error correcting circuits a correct data being selected according to the comparison of the outputs of the two circuit or a majority decision on the outputs of the three circuits. Since the error correction circuit has a very complicated circuit configuration, however, the parallel check system with two or three sets of the error correction circuits has a large-scale circuit structure and thus is unsuitable in an application where a small-size apparatus is required, e.g. an apparatus mounted in a satellite or an airplane.